#ifndef __EKOS_MMU_H__
#define __EKOS_MMU_H__

/* This file is copied from JOS, with slight modification */

#define FRAME_NUM(pa)       (((physaddr_t)(pa)) >> PTX_SHIFT)
#define FRAME_SHIFT         12

// page number field of virtual address
#define PAGE_NUM(la)		(((uintptr_t) (la)) >> PTX_SHIFT)

// page directory index
#define PAGEDIR_IDX(la)       	((((uintptr_t) (la)) >> PDX_SHIFT) & 0x3FF)
// page table index
#define PAGETAB_IDX(la)         ((((uintptr_t) (la)) >> PTX_SHIFT) & 0x3FF)

// offset in page
#define PAGE_OFF(la)	        (((uintptr_t) (la)) & 0xFFF)

// construct linear address from indexes and offset
#define PAGE_ADDR(d, t, o)	((void *) ((d) << PDX_SHIFT | (t) << PTX_SHIFT | (o)))

#define PAGE_ALIGN(addr)        (void *)((uintptr_t) (addr) & ~0xFFF)

/* Page directory and page table constants. */
#define PAGEDIR_COUNT	1024
#define PAGETAB_COUNT	1024

#define PAGE_SIZE	4096 /* bytes mapped by a page */
#define PAGE_SHIFT	12   /* log2(PGSIZE) */

/* bytes mapped by a page directory entry */
#define PAGETAB_SIZE  (PAGE_SIZE * PAGETAB_COUNT) 
#define PAGETAB_SHIFT 22

/* offset of PTX in a linear address */
#define PTX_SHIFT	12
/* offset of PDX in a linear address */
#define PDX_SHIFT	22

/* Page table/directory entry flags. */
#define PTE_P		0x001	// Present
#define PTE_W		0x002	// Writeable
#define PTE_U		0x004	// User
#define PTE_PWT		0x008	// Write-Through
#define PTE_PCD		0x010	// Cache-Disable
#define PTE_A		0x020	// Accessed
#define PTE_D		0x040	// Dirty
#define PTE_PS		0x080	// Page Size
#define PTE_MBZ		0x180	// Bits must be zero

/* The PTE_AVAIL bits aren't used by the kernel or interpreted by the */
/* hardware, so user processes are allowed to set them arbitrarily. */
#define PTE_AVAIL  0xE00
#define PTE_AVAIL1 0x200
#define PTE_AVAIL2 0x400
#define PTE_AVAIL3 0x800

/* Shared memory page */
#define PTE_SHARED PTE_AVAIL1
/* Copy on write */
#define PTE_COW    PTE_AVAIL2
/* Swaped */
#define PTE_SWP    (PTE_AVAIL1 | PTE_AVAIL2)
/* Alloc When Accessed */
#define PTE_AWA    PTE_AVAIL3
/* Managed */
#define PTE_MGR    PTE_AVAIL

#define PTE_SHARED_P(_PTE) (((_PTE) & (PTE_AVAIL1 | PTE_AVAIL2)) == PTE_SHARED)
#define PTE_COW_P(_PTE)    (((_PTE) & (PTE_AVAIL1 | PTE_AVAIL2)) == PTE_COW)
#define PTE_SWP_P(_PTE)    (((_PTE) & (PTE_AVAIL1 | PTE_AVAIL2)) == PTE_SWP)
#define PTE_AWA_P(_PTE)    ((_PTE) & PTE_AWA)
#define PTE_MGR_P(_PTE)    (((_PTE) & PTE_USER) == PTE_MGR)
#define PTE_MGR_PID(_PTE)  ((uint32_t)(PTE_ADDR(_PTE)))

/* a magic entry for page table for locking */
#define PTE_LOCK (0xABCDE000)

/* Only flags in PTE_USER may be used in system calls. */
#define PTE_USER (PTE_AVAIL | PTE_PWT | PTE_PCD | PTE_P | PTE_W | PTE_U)
#define PDE_USER (PTE_AVAIL | PTE_P | PTE_W | PTE_U)

/* address in page table entry */
#define PTE_ADDR(pte)	 ((physaddr_t) ((pte) & ~0xFFF))

/* Control Register flags */
#define CR0_PE		0x00000001	// Protection Enable
#define CR0_MP		0x00000002	// Monitor coProcessor
#define CR0_EM		0x00000004	// Emulation
#define CR0_TS		0x00000008	// Task Switched
#define CR0_ET		0x00000010	// Extension Type
#define CR0_NE		0x00000020	// Numeric Errror
#define CR0_WP		0x00010000	// Write Protect
#define CR0_AM		0x00040000	// Alignment Mask
#define CR0_NW		0x20000000	// Not Writethrough
#define CR0_CD		0x40000000	// Cache Disable
#define CR0_PG		0x80000000	// Paging

#define CR4_PCE		0x00000100	// Performance counter enable
#define CR4_MCE		0x00000040	// Machine Check Enable
#define CR4_PSE		0x00000010	// Page Size Extensions
#define CR4_DE		0x00000008	// Debugging Extensions
#define CR4_TSD		0x00000004	// Time Stamp Disable
#define CR4_PVI		0x00000002	// Protected-Mode Virtual Interrupts
#define CR4_VME		0x00000001	// V86 Mode Extensions

/* Eflags register */
#define FL_CF		0x00000001	// Carry Flag
#define FL_PF		0x00000004	// Parity Flag
#define FL_AF		0x00000010	// Auxiliary carry Flag
#define FL_ZF		0x00000040	// Zero Flag
#define FL_SF		0x00000080	// Sign Flag
#define FL_TF		0x00000100	// Trap Flag
#define FL_IF		0x00000200	// Interrupt Flag
#define FL_DF		0x00000400	// Direction Flag
#define FL_OF		0x00000800	// Overflow Flag
#define FL_IOPL_MASK	0x00003000	// I/O Privilege Level bitmask
#define FL_IOPL_0	0x00000000	//   IOPL == 0
#define FL_IOPL_1	0x00001000	//   IOPL == 1
#define FL_IOPL_2	0x00002000	//   IOPL == 2
#define FL_IOPL_3	0x00003000	//   IOPL == 3
#define FL_NT		0x00004000	// Nested Task
#define FL_RF		0x00010000	// Resume Flag
#define FL_VM		0x00020000	// Virtual 8086 mode
#define FL_AC		0x00040000	// Alignment Check
#define FL_VIF		0x00080000	// Virtual Interrupt Flag
#define FL_VIP		0x00100000	// Virtual Interrupt Pending
#define FL_ID		0x00200000	// ID flag

/* Page fault error codes */
#define FEC_PR		0x1	// Page fault caused by protection violation
#define FEC_WR		0x2	// Page fault caused by a write
#define FEC_U		0x4	// Page fault occured while in user mode

/* Application segment type bits */
#define STA_X		0x8	    // Executable segment
#define STA_E		0x4	    // Expand down (non-executable segments)
#define STA_C		0x4	    // Conforming code segment (executable only)
#define STA_W		0x2	    // Writeable (non-executable segments)
#define STA_R		0x2	    // Readable (executable segments)
#define STA_A		0x1	    // Accessed

/* System segment type bits */
#define STS_T16A	0x1	    // Available 16-bit TSS
#define STS_LDT		0x2	    // Local Descriptor Table
#define STS_T16B	0x3	    // Busy 16-bit TSS
#define STS_CG16	0x4	    // 16-bit Call Gate
#define STS_TG		0x5	    // Task Gate / Coum Transmitions
#define STS_IG16	0x6	    // 16-bit Interrupt Gate
#define STS_TG16	0x7	    // 16-bit Trap Gate
#define STS_T32A	0x9	    // Available 32-bit TSS
#define STS_T32B	0xB	    // Busy 32-bit TSS
#define STS_CG32	0xC	    // 32-bit Call Gate
#define STS_IG32	0xE	    // 32-bit Interrupt Gate
#define STS_TG32	0xF	    // 32-bit Trap Gate

#ifdef __ASSEMBLER__

/*
 * Macros to build GDT entries in assembly.
 */
#define SEG_NULL						\
	 .word 0, 0;						\
	 .byte 0, 0, 0, 0
#define SEG(type,base,lim)								\
	 .word (((lim) >> 12) & 0xffff), ((base) & 0xffff);	\
	 .byte (((base) >> 16) & 0xff), (0x90 | (type)),			\
		  (0xC0 | (((lim) >> 28) & 0xf)), (((base) >> 24) & 0xff)

#else

#include "x86_lock.h"

typedef uint32_t ptab_entry_t;
typedef uint32_t pdir_entry_t;

#define PPAGE_FREE   0
#define PPAGE_CORE   1
#define PPAGE_CACHED 2
#define PPAGE_SHARED 3

struct ppage_t {
     uint16_t   ref_count;
     uint16_t   status;
     mcs_lock_t lock;
     union
     {
		  /* free page list */
		  struct ppage_t *next;
		  /* manager pid */
		  uint16_t owner;
	 };
} __attribute__((packed));

struct memmap_t
{

     union
     {
		  struct { physaddr_t base_l; physaddr_t base_h; };
		  unsigned long long base;
     };

     union
     {
		  struct { physaddr_t end_l; physaddr_t end_h; };
		  unsigned long long end;
     };

     uint32_t flag;
     char foo[4];		/* See MEMMAP_SIZE */
};

struct pf_info_t
{
	 uint32_t proc;
	 uint32_t addr;
	 uint32_t pte;
	 uint32_t err;
};

/* for 32-bit system */
#define MEMMAP_ADDR_OVERFLOW(addr)				\
     ((addr >> 32) > 0)

#define MEMMAP_MAXCOUNT 256

#define MEMMAP_FREE        1
#define MEMMAP_RESERVED    2
#define MEMMAP_RECLAIMABLE 3
#define MEMMAP_NVS         4
#define MEMMAP_BAD         5

#define MEMMAP_BASE  ((void *)(KBASE + 0x1008))
#define MEMMAP_ENTRY ((void *)(KBASE + 0x100c))

// Segment Descriptors
struct segdesc_t {
	 unsigned lim_15_0 : 16;  // Low bits of segment limit
	 unsigned base_15_0 : 16; // Low bits of segment base address
	 unsigned base_23_16 : 8; // Middle bits of segment base address
	 unsigned type : 4;       // Segment type (see STS_ constants)
	 unsigned s : 1;          // 0 = system, 1 = application
	 unsigned dpl : 2;        // Descriptor Privilege Level
	 unsigned p : 1;          // Present
	 unsigned lim_19_16 : 4;  // High bits of segment limit
	 unsigned avl : 1;        // Unused (available for software use)
	 unsigned rsv1 : 1;       // Reserved
	 unsigned db : 1;         // 0 = 16-bit segment, 1 = 32-bit segment
	 unsigned g : 1;          // Granularity: limit scaled by 4K when set
	 unsigned base_31_24 : 8; // High bits of segment base address
};
// Null segment
#define SEG_NULL	(struct segdesc_t){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
// Segment that is loadable but faults when used
#define SEG_FAULT	(struct segdesc_t){ 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0 }
// Normal segment
#define SEG(type, base, lim, dpl) (struct segdesc_t)					\
	 { ((lim) >> 12) & 0xffff, (base) & 0xffff, ((base) >> 16) & 0xff,	\
			   type, 1, dpl, 1, (unsigned) (lim) >> 28, 0, 0, 1, 1,		\
			   (unsigned) (base) >> 24 }
#define SEG16(type, base, lim, dpl) (struct segdesc_t)				\
	 { (lim) & 0xffff, (base) & 0xffff, ((base) >> 16) & 0xff,		\
			   type, 1, dpl, 1, (unsigned) (lim) >> 16, 0, 0, 1, 0,	\
			   (unsigned) (base) >> 24 }

#endif

#define MEMMAP_SIZE  24

/* OFFSETOF(taskstate_t, esp0) */
#define TS_ESP0_OFFSET 4
/* SIZEOF(taskstate_t) */
#define TS_SIZE 104
#define TS_USIZE 128
#define TS_USHIFT 7

#ifndef __ASSEMBLER__

// Task state segment format (as described by the Pentium architecture book)
struct taskstate_t {
	 uint32_t link;	// Old ts selector
	 uintptr_t esp0;	// Stack pointers and segment selectors
	 uint16_t ss0;	//   after an increase in privilege level
	 uint16_t padding1;
	 uintptr_t esp1;
	 uint16_t ss1;
	 uint16_t padding2;
	 uintptr_t esp2;
	 uint16_t ss2;
	 uint16_t padding3;
	 physaddr_t cr3;	// Page directory base
	 uintptr_t eip;	// Saved state from last task switch
	 uint32_t eflags;
	 uint32_t eax;	// More saved state (registers)
	 uint32_t ecx;
	 uint32_t edx;
	 uint32_t ebx;
	 uintptr_t esp;
	 uintptr_t ebp;
	 uint32_t esi;
	 uint32_t edi;
	 uint16_t es;		// Even more saved state (segment selectors)
	 uint16_t padding4;
	 uint16_t cs;
	 uint16_t padding5;
	 uint16_t ss;
	 uint16_t padding6;
	 uint16_t ds;
	 uint16_t padding7;
	 uint16_t fs;
	 uint16_t padding8;
	 uint16_t gs;
	 uint16_t padding9;
	 uint16_t ldt;
	 uint16_t padding10;
	 uint16_t t;		// Trap on task switch
	 uint16_t iomb;	// I/O map base address
};

// Gate descriptors for interrupts and traps
struct gatedesc_t {
	 unsigned gd_off_15_0 : 16;   // low 16 bits of offset in segment
	 unsigned gd_ss : 16;         // segment selector
	 unsigned gd_args : 5;        // # args, 0 for interrupt/trap gates
	 unsigned gd_rsv1 : 3;        // reserved(should be zero I guess)
	 unsigned gd_type : 4;        // type(STS_{TG,IG32,TG32})
	 unsigned gd_s : 1;           // must be 0 (system)
	 unsigned gd_dpl : 2;         // descriptor(meaning new) privilege level
	 unsigned gd_p : 1;           // Present
	 unsigned gd_off_31_16 : 16;  // high bits of offset in segment
};

// Set up a normal interrupt/trap gate descriptor.
// - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate.
// - sel: Code segment selector for interrupt/trap handler
// - off: Offset in code segment for interrupt/trap handler
// - dpl: Descriptor Privilege Level -
//	  the privilege level required for software to invoke
//	  this interrupt/trap gate explicitly using an int instruction
#define SET_GATE(gate, istrap, sel, off, dpl)				\
	 {														\
		  (gate).gd_off_15_0 = (uint32_t) (off) & 0xffff;	\
		  (gate).gd_ss = (sel);								\
		  (gate).gd_args = 0;								\
		  (gate).gd_rsv1 = 0;								\
		  (gate).gd_type = (istrap) ? STS_TG32 : STS_IG32;	\
		  (gate).gd_s = 0;									\
		  (gate).gd_dpl = (dpl);							\
		  (gate).gd_p = 1;									\
		  (gate).gd_off_31_16 = (uint32_t) (off) >> 16;		\
	 }

// Set up a call gate descriptor.
#define SET_CALL_GATE(gate, ss, off, dpl)					\
	 {														\
		  (gate).gd_off_15_0 = (uint32_t) (off) & 0xffff;	\
		  (gate).gd_ss = (ss);								\
		  (gate).gd_args = 0;								\
		  (gate).gd_rsv1 = 0;								\
		  (gate).gd_type = STS_CG32;						\
		  (gate).gd_s = 0;									\
		  (gate).gd_dpl = (dpl);							\
		  (gate).gd_p = 1;									\
		  (gate).gd_off_31_16 = (uint32_t) (off) >> 16;		\
	 }

// Pseudo-descriptors used for LGDT, LLDT and LIDT instructions.
struct pseudodesc_t {
	 uint16_t pd_lim;		// Limit
	 uint32_t pd_base;		// Base address
} __attribute__ ((packed));

#endif /* !__ASSEMBLER__ */


#endif
